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overview the lc65e1104 is an on-chip uveprom version of sanyo? lc651104n/f/l and lc651102n/f/l cmos 4-bit single-chip microcontrollers. the lc65e1104 has the same functions and pin assignment as the lc651104n/f/l and lc651102n/f/l mask rom products, although the a/d characteristics and certain other characteristics differ somewhat. it includes a 4-kb on-chip eprom. the lc65e1104 is provided in dic30s and mfc30s window packages and is ideal for program development and evaluation since program data can be rewritten multiple times. features eprom data option switching the following four lc65e1104 functions can be specified by eprom data: port c and d output levels at reset clock oscillator option clock predivider option watchdog reset option however, note that the port output circuit type cannot be changed. these circuits are always open-drain outputs. internal uveprom capacity: 4096 bytes the lc65e1104 on-chip uveprom can be programmed and verified using a general-purpose eprom programmer. sanyo provides special-purpose 30-to-28-pin adapters (the w65ep1104d for the dic package and the w65ep1104m for the mfc package) to allow commercial eprom programmers to be used with the lc65e1104. data security function pin compatible with the lc651104/1102 mask rom devices instruction cycle time: 0.92 ? to 20 ? (a/d converter cycle time: 0.98 ? to 12 ?) factory shipment: dic-30s (with window), mfc-30s (with window) package dimensions unit: mm 3212-mfc30s unit: mm 3215-dic30s note: these figures are provided for reference purposes and do not include tolerance specifications. official drawings are available on request from your sanyo representative. cmos lsi 73096ha (ot) no. 5221-1/19 preliminaly sanyo: mfc30s [lc65e1104] sanyo: dic30s [lc65e1104] sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan on-chip uveprom 4-bit single-chip microcontroller lc65e1104 ordering number : en * 5221
no. 5221- 2 /19 lc65e1104 lc651104/1102 series organization pin assignment common to dic/mfc usage notes the lc65e1104 was designed for developing and evaluating programs for the lc651104/1102 series microcontrollers. keep the following points in mind when using the lc65e1104. 1. protecting eprom data from uv exposure keep the lc65e1104? package window covered with an opaque seal when using the device. 2. the lc65e1104 differs from the lc651104n/f/l and lc651102n/f/l as listed in the table below. model name pins rom capacity ram capacity package lc651104n/f/l, lc651102n/f/l 30 4 k/2 k 256 w dip30s, dip30s-d, mfp30s lc65e1104 30 4 k 256 w dic30s, mfc30s LC65P1104 30 4 k 256 w dip30s-d, mfp30s note: a/d converter operating supply voltage range: 4.7 to 5.3 v item lc65e1104 lc651104f/1102f lc651104n/1102n lc651104l/1102l i/o circuit configuration open drain (n channel) open drain or pull-up resistor-provided output selectable bit by bit (user mask option) port c and d output high or low selected in 4-bit high or low selected in 4-bit units levels at reset units (by eprom data) (user mask option) resonator rc/ceramic rc/ceramic oscillator (by eprom data) (user mask option) predivider option 1/1, 1/3, 1/4 1/1 only 1/1, 1/3, 1/4 (by eprom data) (user mask option) (user mask option) watchdog reset available/not available available/not available (by eprom data) (user mask option) operating supply 3.0 to 6.0 v * 4.0 t 6.0 v 3.0 to 6.0 v 2.5 to 6.0 v voltage range (v dd ) normal mode current drain mask version + about 3 ma (typical) 2 ma (typical) 1.5 ma (typical) 1.5 ma (typical) low-level input current ?0 a (typical) ?0 a (typical) (res terminal) operating temperature range +10 to +40 c ?0 to +85 c package dic30s (with window) dip30s, dip30s-d mfc30s (with window) mfp30s
pin names system block diagram no. 5221- 3 /19 lc65e1104 osc1, osc2 rc or ceramic oscillator res reset pa0 to pa3 shared-function i/o ports a0 to a3 pc0 to pc3 shared-function i/o ports c0 to c3 pd0 to pd3 shared-function i/o ports d0 to d3 pe0 to pe1 shared-function i/o ports e0 to e1 pf0 to pf3 shared-function i/o ports f0 to f3 pg0 to pg3 shared-function i/o ports g0 to g3 test test int interrupt request pin si serial input pin so serial output pin sck serial clock input/output pin ad0 to ad7 ad converter input pin av+, av ad converter reference voltage input wdr watchdog reset pin note: the si, so, sck, and int pins are shared function pins that are also used as the pf0 to pf3 pins, respectively. ram data memory f flag wr working register ac accumulator alu arithmetic and logic unit dp data pointer e e register ctl control register osc oscillator tm timer rom program memory pc program counter int interrupt control ir instruction register i.dec instruction decoder cf, zsf carry flag, carry save flag zf, zsc zero flag, zero save flag extf external interrupt request flag tmf internal interrupt request flag sts status register
no. 5221- 4 /19 lc65e1104 pin description symbol pins i/o function option at reset prom mode address inputs a9 to a 11 eprom control signal ta identical to pe0 to pe1 serial port: disabled interrupt source: int identical to pe0 to pe1 i/o ports f0 tp f3 identical to pe0 to pe1 * shared with the serial interface and int input. program-selectable si serial input port so serial output port sck serial clock input/output int interrupt request input the serial i/o function can be switched between 4-bit and 8-bit operation under program control. note: * no burst pulse output function is provided. i/o 4 pf0/si/a9 pf1/so/a10 pf2/sck/a11 pf3/int/ta eprom control signal ce address input a0 high-level output (output nch transistor: off) 1. open drain type output i/o port: e0 and e1 input in 4-bit units (ip instruction) output in 4-bit units (op instruction) setting or clearing in single-bit units (spb, rpb instructions) testing in single-bit units (bp and bnp instructions) pe0 provides a continuous burst (64?cyc) function. i/o 2 pe0/ce pe1/wdr/a0 data lines d4 to d7 identical to pc0 to pc3 identical to pc0 to pc3 i/o port: d0 to d3 identical to pc0 to pc3 i/o 4 pd0/d4 pd1/d5 pd2/d6 pd3/d7 data lines d0 to d3 high-level output low-level output (option-selectable) 1. open drain type output 2. output at reset: high 3. output at reset: low 2., 3.: specified in a group of 4 bits i/o port: c0 to c3 identical to pa0 to pa3 * option permits output at reset to be high or low. note: * no standby control function is provided. i/o 4 pc0/d0 pc1/d1 pc2/d2 pc3/d3 address inputs a1 to a4 high-level output (output nch transistor: off) open drain type output i/o port: a0 to a3 input in 4-bit units (ip instruction) output in 4-bit units (op instruction) testing in single-bit units (bp and bnp instructions) setting or clearing in single-bit units (spb and rpb instructions) standby is controlled by pa3 the pa3 pin must be free from chattering during the halt instruction execution cycle. each of these four pins has two functions as listed below. pa0/ad0: ad converter input pin ad0 pa1/ad1: ad converter input pin ad1 pa2/ad2: ad converter input pin ad2 pa3/ad3: ad converter input pin ad3 i/o 4 pa0/ad0/a1 pa1/ad1/a2 pa2/ad2/a3 pa3/ad3/a4 eprom control signal dasec 1. pin 2: rc oscillator external clock 2. pin 2: ceramic oscillator 3. predivider option no predivider 1/3 predivider 1/4 predivider connections for the external rc or ceramic oscillator circuit used as the system clock oscillator. if external clock input is used, leave the osc2 pin open. i o 1 1 osc1/dasec osc2 power supply 1 1 v dd v ss continued on next page.
no. 5221- 5 /19 lc65e1104 continued from preceding page. symbol pins i/o function option at reset prom mode eprom control signal epmod lsi test pin normally connected to v ss 1 test/epmod eprom control signal vpp/oe system reset input connect an external capacitor for power on reset. apply a low level for at least 4 clock cycles for the power-on reset. 1 res/vpp/oe reference voltage input pin for a/d conversion. 1 1 av+ av address inputs a5 to a8 identical to pe0 to pe1 identical to pe0 to pe1 i/o ports g0 to g3 identical to pe0 to pe1 * note: * no burst pulse output function is provided. each of these four pins has two functions as listed below. pg0/ad4: ad converter input pin ad4 pg1/ad5: ad converter input pin ad5 pg2/ad6: ad converter input pin ad6 pg3/ad7: ad converter input pin ad7 i/o 4 pg0/ad4/a5 pg1/ad5/a6 pg2/ad6/a7 pg3/ad7/a8 oscillator circuit option option circuit conditions and notes 1. external clock 2. 2-pin rc osc 3. ceramic oscillator leave the osc2 pin open. predivider option option circuit conditions and notes 1. no predivider (1/1) 2. 1/3 predivider 3. 1/4 predivider applicable to all 3 oscillator options. the oscillator or external clock frequency must not exceed 1444 khz. (lc651104n, lc651102n) the oscillator or external clock frequency must not exceed 4330 khz. (lc651104f, lc651102f) the oscillator or external clock frequency must not exceed 1040 khz. (lc651104l, lc651102l) applicable to the external clock and ceramic oscillator options. the oscillator or external clock frequency must not exceed 4330 khz. applicable to the external clock and ceramic oscillator options. the oscillator or external clock frequency must not exceed 4330 khz. note: the oscillator and predivider options are summarized in the lc651104/1102 semiconductor news.
port c and d reset output level options either of the following two options may be selected for the c and d i/o ports. note that these options are specified in 4- bit units. port output configuration option all shared-function i/o ports have an open-drain output circuit in the lc65e1104. watchdog reset option this option specifies the use of the pe1/wdr pin. this pin can be specified to function either as the normal port pe1 or as the wdr watchdog reset pin. usage notes 1. option specification the su60k.exe program is used for option specification. the option code for the option specification area (addresses 1000 to 100a (hexadecimal)) is created by assembling the output of the su60k.exe program using the sanyo m60k.exe macro assembler and then linking the macro assembler output with the sanyo l60k.exe linker. it is also possible to load data directly into the option specification area. specify options according to the option code creation table on page 8. 2. prom programming lc65e1104 can be programmed with a general-purpose eprom programmer using either the w65ep1104d or w65ep1104m adapter. recommended eprom programmers the intel 27512 (vpp: 12.5 v) high-speed programming method must be used to program this device. the address range must be set to 0 to 100a (hexadecimal) and the dasec jumper must be set to the off position. 3. using the data security function the data security function prevents data already written to the microcontroller's prom from being overwritten. lc651104 data security function procedure move the dasec jumper on the eprom programming pin adapter to the on position. this enables the data security function. attempt to reprogram the eprom. since the data security function is enabled, the eprom programmer will display an error. note that this error is not due to an error in either the programmer or the lsi. no. 5221- 6 /19 lc65e1104 option name conditions 1. output at reset: high all 4 bits of the selected port(s) (c or d or both) 1. output at reset: low all 4 bits of the selected port(s) (c or d or both) option circuit conditions and notes 1. open drain output ports a, c, d, e and f manufacturer eprom programmer advantest r4945, r4944, r4943 or equivalent programmer ando af-9704 aval minato electronics
note: 1. at step 2, the data security function will not operate if all the data at the addresses to be programmed have the value ff (hexadecimal). note: 2. at step 2, the data security function will not apply to (i.e., will not prevent) programming using the sequence blank program verify. note: 3. return the jumper to the off position after executing the data security function. dasec jumper setting no. 5221- 7 /19 lc65e1104
option specification area no. 5221- 8 /19 lc65e1104 rom area bit option specified option/data relationship 7 unused 0 (fixed) 6 watchdog reset 0: disabled, 1: enabled 5 pd output level at reset 0: low level, 1: high level 1000h 4 pc 3 osc predivider (xx = bits 3, bit 2) 00: 1/1, 01: 1/3, 10: 1/4,. 11: unused 2 1 osc resonator (xx = bits 1, bit 0) 00: unused, 01: unused, 10: (2rc, ext), 11: ceramic 0 7 pc3 6 pc2 output configuration 0: od, 1: pu * 5 pc1 1001h 4 pc0 3 pa3 2 pa2 output configuration 0: od, 1: pu * 1 pa1 0 pa0 7 unused 0 (fixed) 6 5 pe1 output configuration 0: od, 1: pu * 1002h 4 pe0 3 pd3 2 pd2 output configuration 0: od, 1: pu * 1 pd1 0 pd0 7 pg3 6 pg2 output configuration 0: od, 1: pu * 5 pg1 1003h 4 pg0 3 pf3 2 pf2 output configuration 0: od, 1: pu * 1 pf1 0 pf0 7 6 1004h 5 to 4 unused 0 (fixed) 100ah 3 2 1 0 note: since all lc65e1104 ports are open-drain output circuits, the pull-up resistor options are ignored. however, the port options m ust be selected when using the lc651104/1102 mask rom products. pu: built-in pull-up resistor output circuit, od: open-drain output circuit
no. 5221- 9 /19 lc65e1104 parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 v output voltage v o osc2 allowable up to the v generated voltage input voltage v i 1 osc1 * 1 ?.3 to v dd + 0.3 v v i 2 test, res, av+, av ?.3 to v dd + 0.3 v input/output voltage v io 1 pc0 to pc3, pd0 to pd3, pe0, pe1, pf0 to pf3 ?.3 to +15 v v io 2 pa0 to pa3, pg0 to pg3 ?.3 to v dd + 0.3 v peak output current i op i/o port ? to +20 ma i oa i/o port: per pin over a 100 ms period ? to +20 ma s i oa 1 pc0 to pc3, pd0 to pd3, pe0, pe1:total current for ?5 to +100 ma average output current pc0 to pc3, pd0 to pd3, and pe0, pe1 * 2 s i oa 2 pf0 to pf3, pg0 to pg3, pa0 to pa3: total current for ?5 to +100 ma pf0 to pf3, pg0 to pg3, and pa0 to pa3 * 2 allowable power dissipation pd max1 ta = +10 to +40 c (dic package) 250 mw pd max2 ta = +10 to +40 c (mfc package) 150 mw operating temperature topr +10 to +40 c storage temperature tstg ?5 to +125 c specifications for lc651104n, 651102n absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit min typ max operating supply voltage v dd v dd 3.0 6.0 v standby supply voltage v st v dd : ram, register hold * 3 1.8 6.0 v v ih 1 port c, d, e, f: output nch tr. off 0.7 v dd +13.5 v v ih 2 port a, g: output nch tr. off 0.7 v dd v dd v high level input voltage v ih 3 int, sck, si: output nch tr. off 0.8 v dd +13.5 v v ih 4 res: v dd = 1.8 to 6 v 0.8 v dd v dd v v ih 5 osc1: external clock mode 0.8 v dd v dd v v il 1 port: output nch tr. off, v dd = 4 to 6 v v ss 0.3 v dd v v il 2 port: output nch tr. off, v dd = 3 to 6 v v ss 0.25 v dd v v il 3 int, sck, si: output nch tr. off, v dd = 4 to 6 v v ss 0.25 v dd v v il 4 int, sck, si: output nch tr. off, v dd = 3 to 6 v v ss 0.2 v dd v low level input voltage v il 5 osc1: external clock mode, v dd = 4 to 6 v v ss 0.25 v dd v v il 6 osc1: external clock mode, v dd = 3 to 6 v v ss 0.2 v dd v v il 7 test: v dd = 4 to 6 v v ss 0.3 v dd v v il 8 test: v dd = 3 to 6 v v ss 0.25 v dd v v il 9 res: v dd = 4 to 6 v v ss 0.25 v dd v v il 10 res: v dd = 3 to 6 v v ss 0.2 v dd v operating frequency fop when the 1/3 or 1/4 predivider option is selected, 200 1444 khz (cycle time) (tcyc) clock must not exceed 4.33 mhz. v dd = 3 to 6 v (20) (2.77) ( s) [external clock conditions] frequency text osc1: fig 1, when clock exceeds 1.444 mhz, 200 4330 khz pulse width texth, textl the 1/3 or 1/4 predivider option must be selected. 69 ns rise/fall time textr, textf v dd = 3 to 6 v 50 ns [oscillator guaranteed constants] cext osc1, osc2: fig 2, v dd = 3 to 6 v 270 5% pf 2-pin rc oscillator cext osc1, osc2: fig 2, v dd = 4 to 6 v 270 5% pf rext osc1, osc2: fig 2, v dd = 3 to 6 v 12 1% k rext osc1, osc2: fig 2, v dd = 4 to 6 v 4.7 1% k ceramic fig 3 table 1 allowable operating conditions at ta = +10 to +40 c, v ss = 0 v, v dd = 3.0 to 6.0 v
no. 5221- 10 /19 lc65e1104 parameter symbol conditions ratings unit min typ max i ih 1 port c, d, e, f: output nch tr. off (including off leak +5.0 a current of nch tr.), v in = +13.5 high-level input current i ih 2 port a, g: output nch tr. off (including off leak +5.0 a current of nch tr.), v in = v dd i ih 3 osc1: external clock mode, v in = v dd +1.0 a i il 1 port: output nch tr. off, v in = v ss ?.0 a low-level input current i il 2 res: v in = v ss ?50 ?0 a i il 3 osc1: external clock mode, v in = v ss ?.0 a v ol 1 port: i ol = 10 ma, v dd = 4.0 to 6.0 v 1.5 v low-level output current v ol 2 port: i ol = 1 ma, i ol of each port; 1 ma or less 0.5 v v dd = 3.0 to 6.0 v [schmitt characteristics] hysteresis voltage vhis 0.1 v dd v high-level threshold voltage vth res, int, sck, si, osc1 of schmitt type * 4 0.4 v dd 0.8 v dd v low-level threshold voltage vtl 0.2 v dd 0.6 v dd v [current dissipation] 2-pin rc oscillator iddop1 v dd : output nch tr. off at operating, port = v dd , 4.5 6 ma fig. 2, fosc = 900 khz (typ) iddop2 v dd : fig 3, 4 mhz, 1/3 predivider 4.5 7 ma ceramic oscillator iddop3 v dd : fig 3, 4 mhz, 1/4 predivider 4.5 6 ma iddop4 v dd : fig 3, 400 khz 4.0 4.5 ma iddop5 v dd : fig 3, 800 khz 4.5 6 ma v dd : 200 khz to 1444 khz, 1/1 predivider; external clock iddop6 600 khz to 4330 khz, 1/3 predivider; 4.5 7 ma 800 khz to 4330 khz, 1/4 predivider standby mode iddst v dd : output nch tr. off, v dd = 6 v 0.05 10 a v dd : port = v dd , v dd = 3 v 0.025 5 a [oscillator characteristics] osc1, osc2: fig 3, fo = 400 khz 384 400 416 khz osc1, osc2: fig 3, fo = 800 khz 768 800 832 khz ceramic osc frequency fcfosc * 5 osc1, osc2: fig 3, fo = 1 mhz 960 1000 1040 khz osc1, osc2: fig 3, fo = 4 mhz, 1/3 predivider, 3840 4000 4160 khz 1/4 predivider fig 4, fo = 400 khz 10 ms stabilization tcfs fig 4, fo = 800 khz, 1 mhz, 4 mhz, 1/3 predivider, 10 ms 1/4 predivider osc1, osc2: fig. 2, cext = 270 pf 5%, 666 900 1334 khz 2-pin rc oscillator fmosc fig. 2, rext = 4.7 k 1%, v dd = 4 to 6 v frequency osc1, osc2: fig. 2, cext = 270 pf 5%, 283 400 717 khz fig. 2, rext = 12 k 1%, v dd = 3 to 6 v [pull-up resistance] i/o port res: ru res: v in = v ss , v dd = 5 v 50 100 250 k [external reset characteristics] reset time trst see fig. 5 pin capacitance c p f = 1 mhz. v in = v ss for all pins other than those 10 pf being tested. [serial clock] input clock cycle time tckcy1 sck: fig. 6 3.0 s output clock cycle time tckcy2 sck: fig. 6 64 tcyc * 6 s input clock low-level pulse width tckl1 sck: fig. 6 1.0 s output clock low-level pulse width tckl2 sck: fig. 6 32 tcyc s input clock high-level pulse width tckh1 sck: fig. 6 1.0 s output clock high-level pulse width tckh2 sck: fig. 6 32 tcyc s [serial input] data setup time tick si: specified from the rising edge of sck. fig. 6 0.4 s data hold time tcki 0.4 s electrical characteristics at ta = +10 to +40 c, v ss = 0 v, v dd = 3.0 to 6.0 v continued on next page.
no. 5221- 11 /19 lc65e1104 continued from preceding page. parameter symbol conditions ratings unit min typ max [serial output] output delay time tcko so: specified from the falling edge of sck. 0.6 s nch od only, external 1k , external 50 pf, fig. 6 [pulse output] period tpcy 64 tcyc s high-level pulse width tph 32 tcyc s 10% low-level pulse width tpl 32 tcyc s 10% [ad conversion characteristics] resolution v dd = 4.7 to 5.3 v 8 bits absolute accuracy av+ = v dd , av?= v ss , v dd = 4.7 to 5.3 v 1 2 lsb ad speed 1/1, at 26 tcyc, v dd = 4.7 to 5.3 v 72 (tcyc 312 (tcyc conversion time tcad = 2.77 s) = 12 s) s ad speed 1/2, at 51 tcyc, v dd = 4.7 to 5.3 v 141 (tcyc 612 (tcyc = 2.77 s) = 12 s) reference input voltage av+ av+: v dd = 4.7 to 5.3 v av v dd v av av? v dd = 4.7 to 5.3 v v ss av+ reference input current range irif av+, av? av+ = v dd , v dd = 4.7 to 5.3 v, av?= v ss 75 150 300 a analog input voltage range vain ad0 to ad7: v dd = 4.7 to 5.3 v av av+ v port pins ad0 to ad7 1 including output off leakage current. vain = v dd , analog port input current iain v dd = 4.7 to 5.3 v a port pins ad0 to ad7 vain = v ss , v dd = 4.7 to 5.3 v ? [watchdog timer] cw wdr: v dd = 3 to 6 v 0.1 5% f guaranteed constant * 7 rw wdr: v dd = 3 to 6 v 680 1% k ri wdr: v dd = 3 to 6 v 100 1% clear time (discharge) twct wdr: fig. 8, v dd = 3 to 6 v 100 s clear time (charge) twccy wdr: fig. 8, v dd = 3 to 6 v 36 ms cw wdr: v dd = 4 to 6 v 0.047 5% f guaranteed constant * 7 rw wdr: v dd = 4 to 6 v 680 1% k ri wdr: v dd = 4 to 6 v 100 1% clear time (discharge) twct wdr: fig. 8, v dd = 4 to 6 v 40 s clear time (charge) twccy wdr: fig. 8, v dd = 4 to 6 v 18 ms pe0: fig. 7, tcyc = 4 system clock period, nch od only, external 1 k , external 50 pf note: 1. the lc65e1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 4 with ci rcuit constants in the guaranteed constants ranges is driven from within the ic. 2. average over a 100 ms period 3. the operating supply voltage v dd must be held until standby mode is enterd after the execution of a halt instruction. the pa3 pin must be free from chattering during the halt instruction cycle. 4. the osc1 pin input circuit has schmitt trigger characteristics when the 2-terminal rc oscillator option or the external clock o scillator option is selected. 5. fcfosc: oscillator frequency. the center frequency of a ceramic oscillator has a tolerance range of about 1% around the nominal value specified by the manufacturer of the oscillator element. for details, refer to the specifications of the ceramic resonator. 6. tcyc = 4 system clock period 7. if the lc65e1104 is used in an environment subject to condensation, leakage between pe1 and adjacent pins and leakage associate d with external rca circuits require special attention.
fig. 1 external clock input waveform fig. 2 2-pin rc oscillator circuit fig. 3 ceramic oscillator no. 5221- 12 /19 lc65e1104 fig. 4 oscillator stabilization period
table 1 constants guaranteed for ceramic resonator oscillator no. 5221- 13 /19 lc65e1104 4 mhz (murata) c1 33 pf 10% csa4.00mg c2 33 pf 10% cst4.00mgw (built-in c) r 0 4 mhz (kyocera) c1 33 pf 10% kbr4.0 msa c2 33 pf 10% kbr4.0mks (built-in c) r 0 1 mhz (murata) c1 100 pf 10% csb1000j c2 100 pf 10% r 2.2 k 1 mhz (kyocera) c1 100 pf 10% kbr1000f c2 100 pf 10% r 0 k 800 khz (murata) c1 100 pf 10% csb800j c2 100 pf 10% r 2.2 k 800 khz (kyocera) c1 220 pf 10% kbr800f c2 220 pf 10% r 0 k 400 khz (murata) c1 220 pf 10% csb400p c2 220 pf 10% r 2.2 k 400 khz (kyocera) c1 330 pf 10% kbr400bk c2 330 pf 10% r 0 k fig. 5 reset circuit note: when the rise time of the power supply is close to 0, the reset time will be between 10 and 100 ms for a cres of 0.5 f. if the rise time of the power supply is significantly longer, the value of cres must be increased so that the reset time will be 10 ms or longer. note: the constants above are preliminarlly. final ratings will be fixed after evaluation. fig. 6 serial input /output timing fig. 7 pulse output timing at port pe0
note: 1. twcct: the charge time due to the time constant of the external cw, rw, and r1 components 2. twct: the discharge time due to program operation fig. 8 watchdog timer waveform no. 5221- 14 /19 lc65e1104
no. 5221- 15 /19 lc65e1104 for lc651104f, 651102f absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 v output voltage v o osc2 allowable up to the v generated voltage input voltage v i 1 osc1 * 1 ?.3 to v dd + 0.3 v v i 2 test, res, av+, av ?.3 to v dd + 0.3 v input/output voltage v io 1 pc0 to pc3, pd0 to pd3, pe0, pe1, pf0 to pf3 ?.3 to +15 v v io 2 pa0 to pa3, pg0 to pg3 ?.3 to v dd + 0.3 v peak output current i op i/o port ? to +20 ma i oa i/o port: per pin over a 100 ms period ? to +20 ma s i oa 1 pc0 to pc3, pd0 to pd3, pe0, pe1:total current for ?5 to +100 ma average output current pc0 to pc3, pd0 to pd3, and pe0, pe1 * 2 s i oa 2 pf0 to pf3, pg0 to pg3, pa0 to pa3: total current for ?5 to +100 ma pf0 to pf3, pg0 to pg3, and pa0, pa3 * 2 allowable power dissipation pd max1 ta = +10 to +40 c (dic package) 250 mw pd max2 ta = +10 to +40 c (mfc package) 150 mw operating temperature topr +10 to +40 c storage temperature tstg ?5 to +125 c parameter symbol conditions ratings unit min typ max operating supply voltage v dd v dd 4.0 6.0 v standby supply voltage vst v dd : ram, register hold * 3 1.8 6.0 v v ih 1 port c, d, e, f: output nch tr. off 0.7 v dd +13.5 v v ih 2 port a, g: output nch tr. off 0.7 v dd v dd v high-level input voltage v ih 3 int, sck, si: output nch tr. off 0.8 v dd +13.5 v v ih 4 res: v dd = 1.8 to 6.0 v 0.8 v dd v dd v v ih 5 osc1: external clock mode 0.8 v dd v dd v v il 1 port: output nch tr. off v ss 0.3 v dd v v il 2 int, sck, si: output nch tr. off v ss 0.25 v dd v low-level input voltage v il 3 osc1: external clock v ss 0.25 v dd v v il 4 test v ss 0.3 v dd v v il 5 res v ss 0.25 v dd v operating frequency (cycle time) fop (tcyc) 200 (20) 4330 (0.92) khz ( s) [external clock conditions] frequency text 200 4330 khz pulse width texth, textl osc1: fig. 1 69 ns rise/fall time textr, textf osc1: fig. 1 50 ns oscillation guaranteed constants fig. 2 see table 1 ceramic resonator oscillator allowable operating conditions at ta = +10 to +40 c, v ss = 0 v, v dd = 4.0 to 6.0 v
no. 5221- 16 /19 lc65e1104 parameter symbol conditions ratings unit min typ max i ih 1 port c, d, e, f: output nch tr. off, (including the nch. +5.0 a transistor off state leakage current.), v in = +13.5 high-level input current i ih 2 port a, g: output nch tr. off, (including the nch. +5.0 a transistor off state leakage current.), v in = v dd i ih 3 osc1: external clock mode, v in = v dd +1.0 a i il 1 port of od type: output nch tr. off, v in = v ss ?.0 a low-level input current i il 2 res: v in = v ss ?50 ?0 a i il 3 osc1: external clock mode, v in = v ss ?.0 a low-level output voltage v ol 1 port: i ol = 10 ma 1.5 v v ol 2 port: i ol = 1 ma, i ol of each port; 1 ma or less 0.5 v [schmitt characteristics] hysteresis voltage vhis 0.1 v dd v high-level threshold voltage vth res, int, sck, si, osc1 of schmitt type * 4 0.4 v dd 0.8 v dd v low-level threshold voltage vtl 0.25 v dd 0.6 v dd v [current drain] ceramic resonator oscillator iddop1 5 8 ma external clock iddop2 5 8 ma standby mode iddst v dd : output nch tr. off, v dd = 6 v 0.05 10 a v dd : port = v dd , v dd = 3 v 0.025 5 a [oscillator characteristics] ceramic resonator oscillator fcfosc osc1, osc2: fig.2, fo = 4 mhz * 5 3840 4000 4160 khz frequency stabilization time tcfs fig. 3, fo = 4 mhz 10 ms [pull-up resistance] i/o port res ru res: v in = v ss , v dd = 5 v 50 100 250 k [external reset characteristics] reset time trst see fig. 4 pin capacitance c p f = 1 mhz. v in = v ss for all pins other than those 10 pf being tested. [serial clock] input clock cycle time tckcy1 sck: fig. 5 2.0 s output clock cycle time tckcy2 sck: fig. 5 64 tcyc * 6 s input clock low-level pulse width tckl1 sck: fig. 5 0.6 s output clock low-level pulse width tckl2 sck: fig. 5 32 tcyc s input clock high-level pulse width tckh1 sck: fig. 5 0.6 s output clock high-level pulse width tckh2 sck: fig. 5 32 tcyc s [serial input] data setup time tick si: specified from the rising edge of sck. fig. 5 0.2 s data hold time tcki 0.2 s [serial output] output delay time tcko so: specified from the falling edge of sck. nch od 0.4 s only, external 1 k , external 50 pf, fig.5 [pulse output] period tpcy 64 tcyc s high-level pulse width tph 32 tcyc s 10% low-level pulse width tpl 32 tcyc s 10% pe0: fig. 6, tcyc = 4 system clock period, nch od only, external 1 k , external 50 pf v dd : fig. 2, 4 mhz, 200 khz to 4330 khz * note: * output nch tr. off at operating mode, port = v dd electrical characteristics at ta = +10 to +40 c, v ss = 0 v, v dd = 4.0 to 6.0 v continued on next page.
no. 5221- 17 /19 lc65e1104 continued from preceding page. parameter symbol conditions ratings unit min typ max [ad conversion characteristics] resolution v dd = 4.7 to 5.3 v 8 bits absolute accuracy av+ = v dd , av?= v ss , v dd = 4.7 to 5.3 v 1 2 lsb ad speed 1/1, at 26 tcyc, v dd = 4.7 to 5.3 v 25 (tcyc 312 (tcyc s conversion time tcad = 0.98 s) = 12 s) ad speed 1/2, at 51 tcyc, v dd = 4.7 to 5.3 v 50 (tcyc 612 (tcyc s = 0.98 s) = 12 s) reference input voltage av+ av+: v dd = 4.7 to 5.3 v av v dd v av av? v dd = 4.7 to 5.3 v v ss av+ reference input current range irif av+, av? av+ = v dd , v dd = 4.7 to 5.3 v, av?= v ss 75 150 300 a analog input voltage range vain ad0 to ad7: v dd = 4.7 to 5.3 v av av+ v port pins ad0 to ad7 1 including output off leakage current. vain = v dd , analog port input current iain v dd = 4.7 to 5.3 v a port pins ad0 to ad7 ? vain = v ss , v dd = 4.7 to 5.3 v [watchdog timer] cw wdr 0.01 5% f guaranteed constants rw wdr 680 1% k ri wdr 100 1% clear time (discharge) twct wdr: fig. 7 10 s clear time (charge) twccy wdr: fig. 7 42 ms note: 1. the lc65e1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 2 with ci rcuit constants in the guaranteed constants ranges is driven internally. 2. average over a period of 100 ms. 3. the operating supply voltage v dd must be held until standby mode is entered after the execution of a halt instruction. the pa3 pin must be free from chattering during the halt instruction execution cycle. 4. the osc1 pin input circuit has schmitt trigger characteristics when the external clock oscillator option is selected. 5. fcfosc: oscillator frequency 6. tcyc = 4 system clock period 7. if the lc65e1104 is used in an environment subject to condensation, leakage between pe1 and adjacent pins and leakage associate d with external rca circuits require special attention. fig. 1 external clock input waveform
fig. 2 ceramic oscillator circuit fig. 3 oscillator stabilization period fig. 5 serial input /output timing table 1 constants guaranteed for ceramic resonator oscillator no. 5221- 18 /19 lc65e1104 note: the constants above are preliminarlly. final ratings will be fixed after evaluation. 4 mhz (murata) c1 33 pf 10% csa4.00mg c2 33 pf 10% cst4.00mgw (built-in c) r 0 4 mhz (kyocera) c1 33 pf 10% kbr4.0 msa c2 33 pf 10% kbr4.0mks (built-in c) r 0 fig. 4 reset circuit note: when the rise time of the power supply is close to 0, the reset time will be between 10 and 100 ms for a cres of 0.5 f. if the rise time of the power supply is significantly longer, the value of cres must be increased so that the reset time will be 10 ms or longer.
no. 5221- 19 /19 lc65e1104 fig. 6 pulse output timing at port pe0 note: 1. twccy: the charge time due to the time constant of the external cw, rw, and r1 components 2. twct: the discharge time due to program operation fig. 7 watchdog timer waveform this catalog provides information as of december, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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